`timescale 1ns / 1ps


module sims(

    );
    reg aclk, mclk, rst_n, tready;
    integer f1, r;

    initial begin
        aclk = 0;
        forever #100 aclk = ~aclk;
    end

    initial begin
        mclk = 0;
        forever #5 mclk = ~mclk;
    end

    initial begin
        f1 = $fopen("C:\\Users\\ZGH\\Desktop\\test\\a.txt", "r");
        rst_n = 1;
        #800 rst_n = 0;
        #800 rst_n = 1;
    end

    reg bd;
    always @(posedge aclk or negedge rst_n) begin
        if (!rst_n) begin
            bd <= 0;
        end else begin
            $fscanf(f1, "%d", r);
            if (r == 0) begin
                bd <= 0;
            end else begin
                bd <= 1;
            end
        end
    end

    wire[31:0] tdata;
    wire tvalid;

    always @(posedge mclk or negedge rst_n) begin
        if (!rst_n) begin
            tready <= 0;
        end else begin
            if (tvalid) begin
                tready <= 1;
            end else begin
                tready <= 0;
            end
        end
    end


    mic_pdm2pcm_v1_0 
    #(
        .FOSR (64 ),
        .FORD (5 )
    )
    u_mic_pdm2pcm_v1_0(
    	.mic_bit_data   (bd   ),
        .mic_clk        (aclk        ),
        .mic_resetn     (rst_n     ),
        .m_axis_aclk    (mclk    ),
        .m_axis_aresetn (rst_n ),
        .m_axis_tvalid  (m_axis_tvalid  ),
        .m_axis_tready  (tready  ),
        .m_axis_tdata   (tdata   ),
        .m_axis_tlast   (m_axis_tlast   )
    );
    
endmodule
